A synchronized switched vertical deflection circuit is shown in U.S. Pat. No. 4,048,544 which is hereby incorporated by reference into the present application. In this patent, first and second controllable switching stages are respectively connected between a source of horizontal retrace pulses and a capacitor connected across the vertical deflection windings. The currents through the two switching stages are of opposite polarity. One switching stage charges the capacitor in a first polarity with pulses of current of gradually decreasing amplitude and duration during a first portion of the vertical deflection interval and the other switching stage charges the capacitor in the opposite polarity with pulses of gradually increasing amplitude and duration during a second portion of the vertical deflection interval. The capacitor then supplies the required energizing current to the vertical deflection winding. In order that the two controllable switching stages operate as detailed above, the voltages applied to the control electrodes of the controllable switches must be varied accordingly. For this purpose, a two-channel multistage control circuit is provided. The output stage of each channel consists of a pulse width modulator, but at least one of the signals applied to the pulse width modulator must undergo a considerable amount of processing before being applied thereto.